Alumni
R. Bogdan Staszewski
Ph.D
Digital Deep Sub-Micron Frequency- Synthesis for RF Wireless Applications
Associate Professor of Microelectronics
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Oren Eliezer
Ph.D
A Phase Domain Approach for Mitigation- of Self-Interference in a Transmitter
Xtendware,Inc.
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Uming Ko
Ph.D
Techniques for the Design of Low Power Processors
Texas Instruments
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Imtinan Elahi
Ph.D
Robust Receiver Design Using Digitally-Intensive Techniques to Overcome Analog-Impairments
Icera
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Ioannis Syllaios
Ph.D
Wide-band all-digital PLL
Broadcom
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Naveen Yanduru
Ph.D
RF Receiver Front-Ends in Deep Sub-Micron CMOS for Multi-Band and Multi-Mode Applications
Samsung
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Viral Parikh
Ph.D
All Digital Quadrature Modulator for- Wideband Wireless Transmitters
Texas Instruments
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Raghunath Cherukuri
Ph.D
Code-Aided Adaptive Decorrelator for IQ- Imbalance Compensationin Iterative-Receivers
CodEPhy, Inc
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NS Nagaraj
Ph.D
Interconnect Modeling, Signal Integrity- and Reliability Analysis for Deep- Sub-Micron Integrated Circuits
Texas Instruments
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Chitaranjan K. Singh
Ph.D
Design of High Performance MIMO- Receiver: Algorithms and VLSI- Architectures
University of Arkansas
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Sharat Prasad
Ph.D
Switch Algorithms and Architectures for- Flow Control of the Available- Bit Rate ATM Service
CISCO
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Sunilduth K. Kanigere
MSEE
Current-mode analog FFT
Intel
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Arunkumar Nehrur Ravi
MSEE
A Wavelet Based Low Power H.264 Encoder and Decoder
Texas Instruments
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Mayank Bhatnagar
MSEE
Implementing Single Electron Device in- Standard CMOS Process
Texas Instruments
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Dhaval Shah
MSEE
Digital Controller for DC-DC Boost Converter
Texas Instruments
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Srinivas Swaminathan
MSEE
Probabilistic Analysis of Noise Effects in- Digital Circuits
Texas Instruments
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Venkata Srinivasan
MSEE
VLSI Architectures for LDPC
Texas Instruments
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Dheera Balasubramanian
MSEE - Fall 2006
Memory module for network on chip- architecture
Texas Instruments
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Rahul Prakash
MSEE - Fall 2006
Phase Noise Reduction of High Speed- Frequency Dividers in Deep Sub Micron- CMOS
Texas Instruments
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Sushma H. Prasad
MSEE
Efficient VLSI Architectures for Matrix Inversion with Application- to MIMO Systems
Texas Instruments
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Chitra Sundaram
MSEE
Effects of Process Variations on High Speed Digital Designs in Sub-100 Nanometer Technologies
Texas Instruments
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Nirav Ginwalla
MSEE
Block Interleaver / Deinterleaver Architectures for Multiple Wireless Standards
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Ramakrishnan Venkatasubramanian
MSEE - Fall 2005
Architectures for High Precision Time to Digital Conversion
Texas Instruments
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Kutraleeshwaran Veerabhadaran
MSEE
Low Leakage Logic Block Architecture for Field- Programmable Gate Arrays
Intel
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Magesh Hariharan
MSEE
A Cache Architecture for IP Forwarding Engines
Qualcomm
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Aleksander Wolfe
MSEE
An Exploration of an FPGA Based Impulse Radio Transceiver for- UWB Communications
Qualcomm
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Srinivas Samudrala
MSEE
Application Interface for Network on Chip Architecture
Motorola
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Ramprasath Vilangudi pitchai
MSEE
Low Power Solutions for Nanometer Technologies
Texas Instruments
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Sumanth Gururajarao Katte
MSEE
Low Leakage Solutions for Ultra Deep-Submicron CMOS
Texas Instruments
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Laxmikantha Holla Vakwadi
MSEE
SOI CMOS Circuits for DSP Applications
Texas Instruments,India
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Prashant Vallur
MSEE
High-Speed Pipelined Adder Circuits in Deep-Submicron CMOS
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Aravind Navada
MSEE
Synchronous and Self-Timed High Speed Arithmetic Circuits
Analog Devices
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Shashank Shastry
MSEE
Design and Evaluation of TSPC Based High Speed CMOS Circuits
SGI
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Abhijeet Chachad
MSEE
QMOS Multiple Valued Logic Design
Texas Instruments
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Kamal Koshy
MSEE
QMOS Digital Logic Circuits
Intel
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Rekha Suryanarayana
MSEE
A VLSI Architecture for an Information Dispersal Algorithm
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Vijayanand Angarai
MSEE
Number Representation Schemes for Energy Efficient-Computer Arithmetic
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Manisha Agarwala
MSEE
Application Specific Enhancement of FPGA Architectures
Texas Instruments
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