Tutorials
5. E. M. Vogel, “Electrical and Reliability Characterization of Advanced MOS Devices,” 2-day Tutorial, Organized by Semyzen, Singapore, July 23-24, 2007
4. E. M. Vogel, ‘Electrical Characterization of MOS Devices with Advanced Gate Stacks,’ Tutorial, 2005 MIGAS International School on Advanced Microelectronics, Physical and Electrical Characterization of Materials and Devices for Silicon Nanoelectronics, (http://www.migas.inpg.fr/), Grenoble, France, June 11-17, 2005. View PDF
3. E. M. Vogel, ‘Characterization, Physical Modeling, and Assessment of Gate Oxide Reliability,’ Tutorial, 2002 IEEE International Reliability Physics Symposium, Dallas, TX, April 7, 2002. View PDF
2. E. M. Vogel, ‘Ultra-thin Gate Oxide Reliability: Past and Present Trends in Characterization, Physical Modeling, and Assessment,’ Tutorial, 2001 IEEE Integrated Reliability Workshop, Lake Tahoe, CA, Oct. 15, 2001. View PDF
1. J. S. Suehle and E. M. Vogel, ‘Thin Gate Oxide Reliability,’ Tutorial, International Reliability Physics Symposium, Apr. 10, 2000. View PDF
Conference and Other Presentations (*Invited)
*48. E. M. Vogel, “Metrology for Emerging Devices and Materials,” American Materials Failure Analysis (AMFA) Workshop, Phoenix, AZ, April 20, 2007. View PDF
*47. E. M. Vogel, “Metrology for Beyond CMOS: Emerging Devices and Materials,” 53rd American Vacuum Society International Symposium, Nano-Manufacturing Topical Conference, San Francisco, CA, Nov. 12-16, 2006. View PDF
*46. E. M. Vogel, “Technology and Metrology for Beyond CMOS,” SEMATECH-SRC Topical Research Conference on Reliability, Austin, TX, Oct. 23, 2006. View PDF
45. Q. Li, S.-M. Koo, C. A. Richter, M. D. Edelstein, J. J. Kopanski, J. S. Suehle, and E. M. Vogel, “Precise Manipulation and Alignment of Single Nanowires for Device Fabrication,” 2006 IEEE Silicon Nanoelectronics Workshop, Honolulu, HI, June 11-12, 2006.
44. S.-M. Koo, C. A. Richter, Q. Li, M. D. Edelstein, and E. M. Vogel, “Schottky-contact silicon nanowire field effect transistor test structures,”2006 IEEE Silicon Nanoelectronics Workshop, Honolulu, HI, June 11-12, 2006.
*43. E. M. Vogel, “Metrology for new microelectronic materials,” American Physical Society Spring Meeting, Baltimore, MD, March 14, 2006. View PDF
*42. E. M. Vogel, “Electrical Characterization of Defects in High-k Gate Dielectrics,” International Semiconductor Device Research Symposium, Bethesda, MD, Dec. 7, 2005. View PDF
41. S.-E. Park, N. V. Nguyen, J. J. Kopanski, J. S. Suehle, and E. M. Vogel, "Comparison of scanning capacitance microscopy and scanning Kelvin probe microscopy in determining two-dimensional doping profiles of Si homostructures", 2005 Ultra Shallow Junction Conference, Daytona Beach, FL.
40. S.-E. Park, St. Jeliazkov, J. J. Kopanski, J. Suehle, E. Vogel, A. Davydov, and H.-K. Shin, "Electrical Characterization of MOS structures and Wide Bandgap Semiconductors by Scanning Kelvin Probe Microscopy", 2005 MRS Spring Meeting, San Francisco, CA.
39. M. Green and E. M. Vogel, “Method for Measuring the Barrier Height at the High-k/Metal Electrode Interface, and Combinatorial Determination of Optimal Metal Gate Electrodes,” SEMATECH Advanced Gate Stack Engineering Working Group Biannual Meeting, Austin, TX, Feb. 14, 2005.
*38. E. M. Vogel and D. Heh, “Depth Profiles of Electrically Active Defects in High-k Gate Stacks Using Charge Pumping,” SEMATECH Advanced Gate Stack Engineering Working Group Biannual Meeting, Austin, TX, Feb. 15, 2005.
*37. E. M. Vogel, ‘A Perspective on the Future of Electronics,’ Nano 2004, Baltimore, MD, Nov. 12, 2004. View PDF
*36. Eric M. Vogel, “Characterization Needs for Emerging Research Materials and Devices,” ITRS Emerging Research Materials Workshop, San Francisco, CA, July 11, 2004.
35. J.-P. Han, S. M. Koo, E. M. Vogel, E. P. Gusev, C. D’Emic, C. A. Richter, J. S. Suehle, “Reverse Short Channel Effects in High-k Gated nMOSFETs,” 13th Workshop on Dielectrics in Microelectronics, Kinsale, Ireland, June 28, 2004. View PDF
34. Curt A. Richter and Eric Vogel, “Computational Needs for Emerging Materials: An Experimental Metrologist's Viewpoint”, Materials Modeling for Emerging Research Materials Workshop, Austin, TX, June 7, 2004.
33. Jin-Ping Han, S.M. Koo, C. A. Richter and Eric Vogel, “Influence of Buffer Layer Thickness on the Ferroelectric Memory window of SrBi2Ta2O9/SiN/Si Structure“, 16th international Symposium on Integrated Ferroelectrics (ISIF’04), Gyeongju, Korea, April 5-8, 2004.
*32. E. M. Vogel, "Challenges of Electrical Measurements of Advanced Gate Dielectrics in MOS Devices," Applied Materials, Feb. 9, 2004.
31. J. Park, C. A. Richter, J. Y. Kim, N. V. Nguyen, J. E. Bonevich, and E. M. Vogel, ‘Characterization of ultrathin amorphous silicon and correlation with crystalline evolution after thermal annealing,’ 2003 MRS Spring Meeting.
*30. E. M. Vogel, ‘Issues with Electrical and Reliability Characterization of Advanced Gate Dielectrics,’ 5th Topical Research Conference on Reliability, Austin, TX, Oct. 28, 2002. View PDF
*29. E. M. Vogel and D. Blackburn, ‘NIST Response to ITRS and Beyond,’ SRC Metrology Needs for Emerging Technologies Workshop, Raleigh, NC, May 3, 2002.
28. D. Heh, E. M. Vogel, J. Bernstein, ‘Relevance of injected hot holes on the breakdown of ultra-thin silicon-dioxide metal-semiconductor devices,’ American Physical Society Spring Meeting, Indianapolis, IN, March 21, 2002.
*27. E. M. Vogel, ‘Issues with Electrical and Reliability Characterization of Advanced Gate Dielectrics,’ Proceedings of the 12th Workshop on Dielectrics in Microelectronics, Grenoble, France, Nov. 20, 2002. View PDF
*26. E. M. Vogel, ‘Degradation and breakdown of ultra-thin silicon dioxide by electron and hole injection,’ IEEE Microelectronics Reliability and Qualification Workshop, Glendale, CA, Dec. 11, 2001. View PDF
25. E. M. Vogel, D. Heh, B. Wang, C. E. Weintraub, J. S. Suehle, M. D. Edelstein, and J. B. Bernstein, ‘Interaction of Electrons with Defects Created by Hot Holes in Ultra-thin Silicon Dioxide,’ 32nd IEEE Semiconductor Interface Specialists Conference, Washington D.C., Nov. 29, 2001.
24. C. A. Richter, E. M. Vogel, A. M. Hodge, and A.R. Hefner, ‘Differences Between Quantum-Mechanical Capacitance-Voltage Simulators,’ 2001 International Conference on Simulation of Semiconductor Processes and Devices, Athens, Greece, Sept. 5-7, 2001.
*23. E. M. Vogel, ‘Issues With the Electrical Characterization and Reliability of MOS Devices With Advanced Gate Dielectrics,’ Materials Research Society Workshop on Dielectric Science & New Functionality in Device Physics for Crystalline Oxides on Semiconductors (COS), Chattanooga, TN, September 11, 2001.
*22. E. M. Vogel, M. D. Edelstein, and J. S. Suehle, ‘Reliability of Ultra-thin Silicon Dioxide Under Substrate Hot-electron, Substrate Hot-hole, and Tunneling Stress,’ 12th Insulating Films on Semiconductors Conference, Udine, Italy, June 20-23, 2001.
View PDF
21. J. S. Suehle, E. M. Vogel, M. D. Edelstein, C. A. Richter, N. V. Nguyen, I. Levin, and D. L. Kaiser, H. Wu, and J. Bernstein, ‘Challenges of High-k Gate Dielectrics for Future MOS Devices,’ 6th International Symposium on Plasma and Process-Induced Damage, Monterey, CA, May 13-15, 2001.
20. E. M. Vogel and J. S. Suehle, ‘Degradation and Breakdown of Ultra-thin Silicon Dioxide Induced by Substrate Hot Hole Injection,’ 31st IEEE Semiconductor Interface Specialists Conference, San Diego, CA, Dec. 7-9, 2000.
*19. E. M. Vogel, M. D. Edelstein, C. A. Richter, N. V. Nguyen, I. Levin, D. L. Kaiser, H. Wu, and J. Bernstein, ‘Issues in High-k Gate Dielectrics for Future MOS Devices,’ IEEE Microelectronics Reliability and Qualification Workshop, Glendale, CA, Oct. 31, 2000. View PDF
18. J. S. Suehle, T. Myers, M. Edelstein, E. M. Vogel, and J. F. Conley, Jr., “The Effects of Ionizing Radiation on Wear-out and Reliability of Thin Gate Oxides,” IEEE Microelectronics Reliability and Qualification Workshop, Glendale, CA, Oct. 31, 2000.
*17. E. M. Vogel, ‘Reliability of Ultra-thin Silicon Dioxide for Future MOS Devices,’ Penn State University, Dept. of Engineering Science, Oct. 4, 2000.
*16. E. M. Vogel, ‘High-k Gate Dielectric Reliability – Issues in Characterization, Physical Modeling, and Assessment,’ Materials Research Society High-k Gate Dielectric Workshop, New Orleans, LA, June 1-2, 2000.
*15. E. M. Vogel, ‘Is technology scaling limited by oxide reliability?’ Panel Member, International Reliability Physics Symposium, Apr. 13, 2000.
14. E. M. Vogel, J. S. Suehle, M. D. Edelstein, B. Wang, Y. Chen, and J. B. Bernstein, ‘Degradation of Ultra-thin SiO2 Under Combined Substrate Hot Electron and Tunneling Stress,’ 30th IEEE Semiconductor Interface Specialists Conference, Charleston, SC, December 2-4, 1999.
13. J. E. Guyer, W. F. Tseng, W. R Thurber, E. M. Vogel, D. A. Gajewski, and J. G. Pellegrino, ‘In Situ Diffuse Reflectance Spectroscopy for Measurement and Control of III-V Molecular Beam Epitaxy,’ Materials Research Society Fall Meeting, Boston, MA, Nov. 29 - Dec. 3, 1999.
*12. Eric M. Vogel, ‘Capacitance and Conductance Characterization of MOS Capacitors with Tunneling Gate Dielectrics,’ SEMATECH Gate Stack Engineering Working Group Meeting, Raleigh, NC, November 11, 1999.
*11. E. M. Vogel, ‘Electrical Characterization and Reliability of MOS Devices with Tunneling Gate Dielectrics,’ IBM, Yorktown Heights, NY, October 14, 1999.
*10. E. M. Vogel, ‘Alternate Dielectric Technology and Metrology,’ University of Delaware, Dept. of Electrical and Computer Engineering, July 13, 1999.
*9. E. M. Vogel, and J. J. Wortman, ‘Properties of N- and P-Channel MOSFETs with Ultrathin RTCVD Oxynitride Gate Dielectrics,’ 1998 Electrochemical Society Spring Meeting, Seattle, Washington, May 2-7, 1999.
*8. E. M. Vogel, ‘Reliability of Ultrathin Oxides for MOS Devices,’ North Carolina State University, Dept. of Electrical and Computer Engineering, Apr. 22, 1999.
7. A. Shanware, H. Z. Massoud, E. Vogel, K. Henson, J. R. Hauser, and J. J. Wortman, ‘MOSFET Substrate Currents due to Valence-Band Tunneling in 15-35 Å, 29th IEEE Semiconductor Interface Specialists Conference, San Diego, CA, December 3-5, 1998.
6. E. M. Vogel, C. E. Weintraub, and J. J. Wortman, ‘Properties of n-Channel and p-Channel MOSFETs with Ultrathin Gate Dielectrics,’ SRC TECHCON ’98, Las Vegas, NV, September 9-11, 1998.
5. E. M. Vogel, J. J. Wortman, and J. R. Hauser, ‘The Use of RTCVD Oxynitrides in Ultra-thin Gate Dielectric Stacks,’ 28th IEEE Semiconductor Interface Specialists Conference, Charleston, SC, December 4-6, 1997.
4. E. M. Vogel, W. K. Henson, P. K. McLarty, J. J. Wortman, and J. R. Hauser, ‘Stacked RTCVD Oxide and Oxynitride Films for Ultrathin Gate Dielectrics,’ 27th IEEE Semiconductor Interface Specialists Conference, San Diego, CA, December 5-7, 1996.
3. E. M. Vogel, W. L. Hill, V. Misra, P. K. McLarty, J. J. Wortman, J. R. Hauser, P. Morfouli, G. Ghibaudo, and T. Ouisse, ‘A self-consistent physical explanation for the mobility behavior of n-channel and p-channel MOSFETs with oxynitride gate dielectrics formed by low pressure rapid thermal chemical vapor deposition,’ 26th IEEE Semiconductor Interface Specialists Conference, Charleston, SC, December 7-9, 1995.
2. P. Morfouli, G. Ghibaudo, E. M. Vogel, W. L. Hill, V. M. Misra, P. K. McLarty, and J. J. Wortman, ‘Electrical and Reliability Properties of Thin Silicon Oxynitride Dielectrics Formed by Low Pressure Rapid Thermal Chemical Vapor Deposition,’ Proceedings of the 7th ESPRIT Workshop on Dielectrics in Microelectronics, Crete, Greece, November, 1995.
1. P. Morfouli, G. Ghibaudo, T. Ouisse, E. M. Vogel, W. L. Hill, V. Misra, P. McLarty, J. J. Wortman, ‘Noise Analysis of MOSFET’s with Ultra Thin Silicon Oxynitride Films Prepared by Low Pressure Rapid Thermal Chemical Vapor Deposition (LPRTCVD)’, Proceedings of the 25th European Solid State Device Research Conference, Hague, Netherlands, September 25-27, 1995.