CMOS Devices and Materials
Traditional scaling of planar, silicon-based CMOS field-effect-transistors (FETs) has been the basis of the semiconductor industry for 30 years. As the lateral dimensions of the FET are scaled downward, the gate capacitance must be increased to reduce short-channel effects and keep at least the same drive current. Historically, this has been accomplished by reducing the thickness of SiO2. Highly doped polysilicon has been used as the gate electrode because it historically exhibited near-metallic properties. The thickness of silicon dioxide or oxynitride in manufacturing today is approximately 1.2 nm. Continued thickness scaling of silicon dioxide is not possible because of the power dissipation associated with tunneling through the dielectric. Furthermore, because of high vertical electric fields, the polysilicon gate electrode exhibits significant depletion that limits the performance of the FET. Therefore, high-k dielectrics such as HfO2, which provide lower leakage current and higher capacitance, and metal gate electrodes, which do not suffer from depletion, are currently in development for the ~45 nm (~2007) technology generation.
These technologies, along with silicon germanium and silicon-on-insulator will likely permit scaling of planar, silicon-based CMOS FETs until ~2010. Beyond ~2010, the use of alternative gate stacks with the reduction of lateral channel dimension will not provide the continued performance increases required by the semiconductor industry. Therefore, non-planar and/or non-silicon-based, CMOS technologies (“Extreme CMOS”) will be required. The two primary technologies we are considering for Extreme CMOS are: 1) high mobility channel materials (e.g., InGaAs and GaSb), and 2) fin (top-down silicon nanowire) FETs. Both of these technologies are attractive because they permit increases in device performance (speed) with slower reductions in lateral and vertical device dimensions.