MATERIALS SCIENCE & ENGINEERING SEMINAR
Friday, April 28th, 2 p.m. to 3:30 p.m., ECS North 2.704
High-k/Metal Gate Stacks Scaling for High Performance MOS Devices
Dr. Manuel Quevedo-Lopez
Texas Instruments Assignee at International SEMATECH
Throughout the history of integrated circuits, shrinking the dimensions of the transistor has required that many difficult challenges be overcome. In particular, it is clear that the current gate dielectric material, SiON, will soon reach its predicted limits, thus presenting a fundamental challenge to continued CMOS scaling [1]. Therefore, the introduction of high-k materials to continue scaling of CMOS devices is imminent.
Before implementing high-k dielectrics in a conventional CMOS process, issues such as degraded mobility at low equivalent oxide thickness (EOT), charge trapping-induced threshold voltage (VTH) instability and bias temperature instability (BTI) [2-8] need to be addressed. Nitrided HfO2 and hafnium silicate (HfSiO) are the leading candidates to replace SiON. However, neither of them has been selected as the material of choice by the semiconductor industry. From the standpoint of thermal stability, HfSiON seems to be desirable [9]. On the other side, HfO2 may be more scalable due to its slightly higher dielectric constant [3].
In this seminar, the scaling limits of atomic layer deposited HfON and HfSiON are presented. The impact of starting interface, film thickness, post-deposition anneal, and metal electrode on EOT scaling is also investigated. Based on the data available, it is shown that HfSiON is a robust dielectric and is scalable to at least 1 nm EOT with 90% mobility and excellent reliability [10].
REFERENCES:
[1] ITRS, Semiconductor Industry Association, San Jose, CA 95129, 2005.
[2] P. D. Kirsch, et al., EESDERC 2005, Grenoble, FR.
[3] J. J. Peterson et al., Electrochem. Solid-State Lett., 7 (8) G164-G167 (2004)
[4 A. Callegari et al., IEDM Tech. Dig. , 825 (2004).
[5] B.H.Lee et al., IEDM Tech. Dig., p.859 (2004).
[6] E. P. Gusev et al., IEDM Tech. Dig., p.729 (2004).
[7] H. R. Harris et al., Proceedings of IRPS, p.80 (2005).
[8] R.Chau et al., EDL v.25,p.408 (2004).
[9] A. Shanware et al., IEDM Tech. Dig., p.38-6 (2003).
[10] M. A. Quevedo-Lopez, IEDM 2005.
BIO:
Manuel Quevedo-Lopez received a Ph.D. degree from the University of North Texas, Denton TX, USA in 2002. He then joined Texas Instruments's Silicon Technology Develoment Group as Member of technical Staff where his research focused on advanced high-k gate dielectric and CMOS isolation technologies. In 2004 He joined SEMATECH in Austin Texas as TI assignee to work on SEMATECH's advanced gate dielectric project. Dr. Quevedo-Lopez is author or co-author of more than 40 publications in peer reviewed journals and 3 US patents issued and 10 more pending.
